GPS Engine Board

1) Full navigation accuracy provided by Standard Positioning Service (SPS). 2) Allows the receiver to track the satellites using up to 12-channel correlators. 3) Dual serial communication channels and user selectable baud rates allow the design with maximum interface capability and flexibility. 4) Optional to supports downloadable firmware code for upgrading the advanced programs. 5) No any initialization setup is required while start to use. 6) Support backup battery to sustain internal clock.

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GPS Engine Board
	1) Full navigation accuracy provided by Standard Positioning Service (SPS). 2) Allows the receiver to track the satellites using up to 12-channel correlators. 3) Dual serial communication channels an

GPS Engine Board
	1) Full navigation accuracy provided by Standard Positioning Service (SPS). 2) Allows the receiver to track the satellites using up to 12-channel correlators. 3) Dual serial communication channels an

Antenna
	1) High LNA Gain up to 27dB 2) Miniaturized to 383812.5 mm3 3) Low Noise figure to 1.5dB 4) Low Current Consumption below 12mA 5) Variable cable length and connectors are available. 6) Water Resist

Antenna
	1) High LNA Gain up to 27dB 2) Miniaturized to 383812.5 mm3 3) Low Noise figure to 1.5dB 4) Low Current Consumption below 12mA 5) Variable cable length and connectors are available. 6) Water Resist

Antenna
	1) High LNA Gain up to 27dB 2) Miniaturized to 383812.5 mm3 3) Low Noise figure to 1.5dB 4) Low Current Consumption below 12mA 5) Variable cable length and connectors are available. 6) Water Resist

GPS Chipset
	1) 32-bit processor with separate instruction and data cache. 2) 16-bit SDRAM, device interface support. 3) Support 2 SDRAM banks. 4) 6 device decoder with programmable base, offset and access wait s

GPS Chipset
	1) 32-bit processor with separate instruction and data cache. 2) 16-bit SDRAM, device interface support. 3) Support 2 SDRAM banks. 4) 6 device decoder with programmable base, offset and access wait s

GPS Chipset
	1) 32-bit processor with separate instruction and data cache. 2) 16-bit SDRAM, device interface support. 3) Support 2 SDRAM banks. 4) 6 device decoder with programmable base, offset and access wait s

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